1. Technical Field
This disclosure relates generally to computer processors, and more particularly to processing instructions that specify multiple destinations.
2. Description of the Related Art
Instruction set architectures for modern processors often include multi-destination instructions. Such instructions may specify multiple destination registers in which a processor should store instruction results. For example, the ARM® instruction set architecture includes long multiply instructions such as UMULL, UMLAL, SMULL, and SMLAL that include two destination register fields in each instruction to indicate where the processor should store a multiply result. Similarly, load-multiple instructions such as ARM® LDM instructions and POWERPC® LMW instructions, for example, indicate a number of destination registers that a processor should load with data from one or more specified memory addresses. Handling multi-destination instructions may require extra hardware in a processor pipeline and/or may slow processor performance.